Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 141

iterate only once or twice and loops of length two that iterate only once
incur two cycles of overhead, because two aborted instructions after the
last iteration are needed to clear the instruction pipeline.
Table 3-10. Pipelined Execution Cycles for Single Instruction
Counter-based Loop with Three Iterations
Cycles 1
Execute
N
Decode N + 1
Fetch N + 2
N is the loop start instruction and N + 2 is the instruction after the loop.
1. Loop count (LCNTR) equals 3
2. No opcode latch or fetch address update; count expired tests true
3. Loop iteration aborts; PC and loop stacks pop
Table 3-11. Pipelined Execution Cycles for Single Instruction
Counter-based Loop with Two Iterations (Two Overhead Cycles)
Cycles 1
Execute 1
N
Decode N + 1
Fetch N + 2
N is the loop start instruction and N + 3 is the instruction after the loop.
1. Loop count (LCNTR) equals 2
2. PC Stack supplies loop start address
3. Count expired tests true
4. Loop iteration aborts; PC and loop stacks pop
ADSP-2126x SHARC Processor Hardware Reference
2
1 N + 1 (Pass 1) N + 1 (Pass 2) N + 1 (Pass 3) N + 2
N + 1
2
N + 1
2 3
N + 1 (Pass 1) N + 1 (Pass 2) NOP
N + 1 N + 1 –>
NOP
2
N + 1 N + 1
Program Sequencer
3 4
N + 1 N + 2
3 N + 3
N + 2
4
N + 1 –>
4 5
NOP
N + 2
3
5
N + 3
N + 4
5 6
NOP N + 2
N + 2 N + 3
N + 3 N + 4
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