Extended-Precision Normal Word Addressing Of Dual-Data - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings
Extended-Precision Normal Word Addressing of
Dual-Data
Figure 5-20 shows the SISD, dual-data, 40-bit extended-precision normal
word addressed access mode. For extended-precision normal word
addressing, the processor treats each data bus as a 40-bit extended-preci-
sion normal word lane. The 40-bit values for the extended-precision
normal word accesses are transferred using the most significant 40 bits of
the PM and DM data bus. The processor drives the lower 24 bits of the
data buses with zeros.
In Figure 5-20, the access targets the
tion. This instruction accesses
with syntax that targets registers
register when using the syntax
PEy
5-50
PEx
WORD X0
and
RX
or
SX
ADSP-2126x SHARC Processor Hardware Reference
registers in a SISD mode opera-
in block 1 and
WORD Y0
in . The example targets a
RY PEx
.
SY
in block 0