Bypass As A One Shot - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

CL OCK INPU T
FO R FRAM E S Y NC
FRAM E S YN C OUT PU T
(INV FS A = 0, S TRO BEA = 0)
FRAM E S YN C OUT PU T
(INV FS A = 1, S TRO BEA = 0)
Figure 13-4. Frame Sync Bypass

Bypass as a One Shot

When the
STROBEA
of the register) is set (= 1), the One Shot option is used. When the
PCG_PW
bit is set (= 1), the frame sync is a pulse with a duration equal to
STROBEx
one period, or one full cycle, of
B that repeats at the beginning of every clock input period. This pulse is
generated during the high period when the
respectively = 0), are cleared or low period when invert bit (
of the input clock.
A strobe period is equal to the period of the normal clock input signal spec-
ified by
FSASOURCE
(bit 30 in the
FSBSOURCE
The output pulse width is equal to the period of the SRU source signal
( for frame sync A and
MISCA2_I
begins at the second rising edge of
clock input. When the
rising edge of
MISCxx_I
input.
For more information, see "Group E Connections – Miscellaneous Sig-
nals" on page 12-23.
ADSP-2126x SHARC Processor Hardware Reference
bit (bit 0 of the
PCG_PW
MISCA2_I
(bit 30 in the
PCG_CTLA_1
register for unit B).
PCG_CTLB_1
MISCB3_I
MISCxx_I
bit is set, the pulse begins at the second
INVFSA/B
coincident or following a falling edge of the clock
Precision Clock Generator
register) or
STROBEB
for unit A and
MISCA3_I
bits (bits 1 or 17,
INVFSA/B
register for unit A) and
for frame sync B). The pulse
following a rising edge of the
bit (bit 16
for unit
= 1)
INVFSA/B
13-11