Data Transfers; Status Information - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

bit controls the configuration of transmit versus receive opera-
SPTRAN
tions. Serial ports can transmit or receive a selectable word length, which
is programmed by the
Length (SLEN)" on page 9-15
companding hardware built in to the A channels that allow sign extension
or zero-filling of upper bits of the serial data word. These configurations
are selected by the
page 9-41 and
endian format (LSB versus MSB first) is selectable by the
register. See
SPCTL
packing of two serial words into a 32-bit word is also selectable. The
bit in the
SPCTL
Unpacking" on page 9-40

Data Transfers

Serial port data can be transferred for use by the processor in two different
methods:
• DMA transfers
• Core-driven single word transfers
DMA transfers can be set up to transfer a configurable number of serial
words between the serial port buffers (
) and internal memory automatically. For more information on
RXSPxB
Sport DMA operations, see
driven transfers use SPORT interrupts to signal the processor core to per-
form single word transfers to/from the serial port buffers (
, and
RXSPxA RXSPxB
details.

Status Information

Serial ports provide status information about data buffers via the
and status bits and error status via
DXS_B
ADSP-2126x SHARC Processor Hardware Reference
bits in the
SLEN
for more details. Serial ports also include
bits in the
DTYPE
"Companding" on page 9-42
"Endian Format" on page 9-40
register controls this option. See
for more details.
"DMA Block Transfers" on page
). See "SPORT Interrupts" on page 9-64
register. See
SPCTL
register. See
SPCTL
for more information. The
for more details. Data
"Data Packing and
, ,
TXSPxA TXSPxB
or
ROVF TUVF
Serial Ports
"Setting Word
"Data Type" on
bit of the
LSBF
PACK
, and
RXSPxA
9-66. Core
,
TXSPxA TXSPxB
for more
DXS_A
bits in the
SPCTL
9-13
,