Pcg Programming Examples - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

PCG Programming Examples

CLOCK INPUT
FOR FRAME SYNC
MISCA2_I
FRAME SYNC OUTPUT
(INVFSA = 0, STROBEA = 1)
FRAME SYNC OUTPUT
(INVFSA = 1, STROBEA = 1)
Figure 13-5. One Shot (Synchronous Clock Input and MISCA2_I)
The second
INVFSA
ter determines whether the falling or rising edge is used. When set (= 1),
this bit selects an active low frame sync, and the pulse comes during the
low period of clock input. When cleared (= 0) this bit is set to active high
frame sync and the pulse comes during the high period of clock input. For
more information on the
page A-147.
PCG Programming Examples
This section provides two programming examples written for the
ADSP-21262 processor. The first listing,
B to output a clock on DAI pin 1 and frame sync on DAI pin 2. The input
used to generate the clock and frame sync is
strates the clock and frame sync divisors, as well as the pulse width and
phase shift capabilities of the PCG.
The second listing,
set up to only generate a clock signal. This clock signal is used as the input
to channel B via the SRU. The clock and frame sync are routed to DAI
pins 1 and 2, respectively, in the same manner as the first example. This
13-12
bit (bit 1) of the Pulse Width Control (
register, refer to
PCG_PW
Listing 13-2, uses both PCG channels. Channel A is
ADSP-2126x SHARC Processor Hardware Reference
PCG_PW
Table A-44 on
Listing 13-1, uses PCG channel
. This example demon-
CLKIN
) regis-