32-Bit Normal Word Addressing Of Dual-Data In Simd Mode - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings
32-Bit Normal Word Addressing of Dual-Data in
SIMD Mode
Figure 5-18 shows the SIMD, dual-data, 32-bit normal word addressed
access mode. For normal word addressing, the processor treats the data
buses as two 32-bit normal word lanes. The explicitly addressed (named in
the instruction) 32-bit values are transferred using the least significant
normal word lane of the PM or DM data bus. The implicitly addressed
(not named in the instruction, but inferred from the address in SIMD
mode) normal word values are transferred using the most significant nor-
mal word lanes of the PM and DM data bus.
In Figure 5-18, the explicit access targets the named registers
and the implicit access targets those register's complementary registers
and . This instruction uses the
SA
mnemonics.
Figure 5-16 shows the data path for one transfer. The processor accesses
normal words sequentially in memory. For more information on arranging
data in memory to take advantage of this access pattern, see
on page 5-76.
5-46
registers with the
PEx
ADSP-2126x SHARC Processor Hardware Reference
and ,
RX RA
SX
and
RX RA
Figure 5-40