Status Stack Register (Sts; Fetch Address Register (Faddr; Decode Address Register (Daddr; Loop Address Stack Register (Laddr - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Status Stack Register (STS)

The register is a status stack register that stores three status registers
STS
( ,
MODE1 ASTATx
tions deep. For the
automatically pushes and pops the status stack. Note the
only be accessed by

Fetch Address Register (FADDR)

The register is a non-memory-mapped, universal register (
FADDR
only). The Fetch Address register is the first stage in the fetch-decode-exe-
cute instruction pipeline and contains the 24-bit address of the instruction
that the DSP fetches from memory on the next cycle.

Decode Address Register (DADDR)

The register is a non-memory-mapped, universal register (
DADDR
only). The Decode Address register is the second stage in the
fetch-decode-execute instruction pipeline and contains the 24-bit address
of the instruction that the DSP decodes on the next cycle.

Loop Address Stack Register (LADDR)

The register is a non-memory-mapped, universal register (
LADDR
only). The Loop Address Stack is six levels deep by 32 bits wide. The
32-bit word of each level consists of a 24-bit loop termination address, a
5-bit termination code, and a 2-bit loop type code.
ADSP-2126x SHARC Processor Hardware Reference
and ). The register is 3x32-bit wide and 15 loca-
ASTATy
and timer interrupts, the sequencer
IRQ2-0
or
push sts pop sts
Registers Reference
STS
instructions.
register can
Ureg
Ureg
Ureg
A-35