Phase Shift Settings - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Phase Shift Settings

The phase shift between clock and frame sync outputs may be pro-
grammed under these conditions:
• The input clock source for the clock generator output and the
frame sync generator output is the same.
• Clock and frame sync are enabled at the same time using a single
atomic instruction.
• Frame sync divisor is an integral multiple of the clock divisor.
If the phase shift is zero, the clock and frame sync outputs rise at the same
time. If the phase shift is one, the frame sync output transitions one input
clock period ahead of the clock transition. If the phase shift is
, the frame sync transitions
DIVISOR – 1
ahead of the clock transitions. This translates to the input clock period
after the clock transition, which further translates to one input clock
period after the clock transition.
Phase shifting is represented as a full 20-bit value so that even when frame
sync is divided by the maximum amount, the phase can be shifted to the
full range, from zero to one input clock short of the period.
13-8 ADSP-2126x SHARC Processor Hardware Reference
input clock periods
DIVISOR – 1