Reset And Clkin - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

r0 = 4096;
lcntr = r0, do pllwait until lce;
pllwait:nop;
ustat2 = dm(PMCTL);
bit clr ustat2 PLLBP;
/* take PLL out of Bypass */
dm(PMCTL) = ustat2;
PMCTL register bit definitions:
/* Power Management Control register (PMCTL) */
#define PLLM8
#define PLLD8
#define INDIV
#define DIVEN
#define CLKOUTEN (BIT_12)
#define PLLBP
#define SPIPDN

RESET and CLKIN

The processor receives its clock input on the
an on-chip phase-locked loop (PLL) to generate its internal clock, which is
a multiple of the
the PLL requires some time to achieve phase lock,
a minimum time period during reset before the
serted. For information on minimum clock setup, see the specific
ADSP-2126x data sheet.
Table 15-3 and
ratios supported by the processor. Note that programs control the PLL
through the
PMCTL
ment Registers" on page
ADSP-2126x SHARC Processor Hardware Reference
/* wait for PLL to lock at new rate
(requirement for modifying multiplier
and setting INDIV bit only) */
(BIT_3) // PLL Multiplier 8
(BIT_7) // PLL Divisor 8
(BIT_8) // Input Divider
(BIT_9) // Enable PLL Divisor
// Mux select for CLKOUT/RESETOUT
(BIT_15) // PLL Bypass mode indication
(BIT_30) // Shutdown clock to SPI
frequency
CLKIN
Table 15-4 show the internal clock to
register. This register is described in
A-65.
pin. The processor uses
CLKIN
(Figure 15-1 on page
CLKIN
RESET
System Design
15-11). Because
must be valid for
signal can be deas-
frequency
CLKIN
"Power Manage-
15-7