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SRU_PBEN3 (0x247B)
Reserved
PBEN20
DAI Port 20
Pin Buffer Enable Input
15 14 13 12 11 10
1
PBEN18
DAI Port 18
Pin Buffer Enable Input
PBEN17
DAI Port 17
Pin Buffer Enable Input
Figure A-55. SRU_PBEN3
Table A-39. Group F Sources – Pin Output Enable
Selection Code
000000 (0x0)
000001 (0x1)
000010 (0x2)
000011 (0x3)
000100 (0x4)
000101 (0x5)
000110 (0x6)
000111 (0x7)
001000 (0x8)
ADSP-2126x SHARC Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
1
1
0
1
9
8
1
1
1
0
1
1
1
Source Signal
LOW
HIGH
MISCA0_O
MISCA1_O
MISCA2_O
MISCA3_O
MISCA4_O
MISCA5_O
SPORT0_CLK_PBEN_O
Registers Reference
0
1
1
1
0
0
0
7
6
5
4
3
2
1
0
1
0
0
1
1
0
1
1
Description
Select Logic Level Low (0) as the source
Select Logic Level High (1) as the source
Assign Miscellaneous Control A0 Output to a
pin
Assign Miscellaneous Control A1 Output to a
pin
Assign Miscellaneous Control A2 Output to a
pin
Assign Miscellaneous Control A3 Output to a
pin
Assign Miscellaneous Control A4 Output to a
pin
Assign Miscellaneous Control A5 Output to a
pin
Select Serial Port 0 Clock Output Enable as
the source
1
PBEN19
DAI Port 19
Pin Buffer Enable Input
PBEN16
DAI Port 16
Pin Buffer Enable Input
A-139
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