Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 15

Selecting Frame Sync Options (DIFS) ............................... 9-16
Enabling SPORT DMA (SDEN) ....................................... 9-17
Interrupt-Driven Data Transfer Mode ............................ 9-17
DMA-Driven Data Transfer Mode ................................. 9-17
2
I S Mode .............................................................................. 9-18
2
I S Mode Control Bits ...................................................... 9-20
Setting the Internal Serial Clock and Frame Sync Rates ...... 9-20
2
I S Control Bits ................................................................ 9-20
Setting Word Length (SLEN) ............................................ 9-21
Enabling SPORT Master Mode (MSTR) ........................... 9-21
Selecting Transmit and Receive Channel Order (FRFS) ...... 9-21
Selecting Frame Sync Options (DIFS) ............................... 9-22
Enabling SPORT DMA (SDEN) ....................................... 9-22
Interrupt-Driven Data Transfer Mode ............................ 9-23
DMA-Driven Data Transfer Mode ................................. 9-23
Multichannel Operation ........................................................ 9-24
Frame Syncs in Multichannel Mode ................................... 9-26
Active State Multichannel Receive Frame Sync Select ..... 9-27
Multichannel Mode Control Bits ....................................... 9-27
Receive Multichannel Frame Sync Source ....................... 9-29
Active State Transmit Data Valid ................................... 9-29
Multichannel Status Bits ................................................ 9-29
Channel Selection Registers ........................................... 9-30
SPORT Loopback ............................................................. 9-32
ADSP-2126x SHARC Processor Hardware Reference
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