Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 560

Frame Sync Outputs
through the
MISCA4_I
SRU_EXT_MISCA
Registers (SRU_EXT_MISCx, Group E)" on page A-132.
Synchronization with the external clock is enabled by setting bit 25 of the
register for PCGA frame sync output and bit 10 of the
SRU_CLK2
register for PCGB frame sync output.
Routing Control Registers (SRU_CLKx, Group A)" on page A-114.
phase must be programmed to three, so that the rising edge of the external
clock is in sync with the frame sync. Programming should occur in the fol-
lowing order:
1. Program PCG control registers
SRU_CLK3
2. Enable the clock, frame sync, or both. In other words, program all
the values before enabling the PCG (clock and frame sync).
Since the rising edge of the external clock is used to synchronize
with the frame sync, the frame sync output is not generated until a
rising edge of the external clock is sensed.
PCGx_CLKIN
EXT CLK
(INPUT)
FSA
(OUTPUT)
Figure 13-2. Clock Output Synchronization with External Clock
The clock output cannot be aligned with the rising edge of the external
clock as there is no phase programmability. Once
enabled, by programming bit 31 of
13-6
(for PCGA) and
register. For more information, see "Miscellaneous SRU
as mentioned above.
ADSP-2126x SHARC Processor Hardware Reference
(for PCGB) signals of the
MISCA5_I
For more information, see "Clock
,
SRU_EXT_MISCA
CLKA
and
PCG_CTLA_0 PCG_CTLB_0
SRU_CLK3
The
and
SRU_CLK2
and have been
CLKB
registers