Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 295

A channel interrupt mask in the
, and
DAI_IRPTL_RE
interrupt is to be serviced or not. When an interrupt is masked, it is
latched but not serviced.

By clearing a channel's
mask the DMA complete interrupt for a DMA process within a
chained DMA sequence.
The I/O processor can also generate interrupts for I/O port operations
that do not use DMA. In this case, the I/O processor generates an inter-
rupt when data becomes available at the receive buffer or when the
transmit buffer is not full (when there is room for the core to write to the
buffer). Generating interrupts in this manner lets programs implement
interrupt-driven I/O under control of the processor core. Care is needed
because multiple interrupts can occur if several I/O ports transmit or
receive data in the same cycle.
Table 7-1. DMA Interrupt Vector Locations
Associated Register(s)
IRPTL/IMASK
LIRPTL
IRPTL/IMASK
LIRPTL
IRPTL/IMASK
LIRPTL
IRPTL/IMASK
LIRPTL
IRPTL/IMASK
LIRPTL
IRPTL/IMASK
ADSP-2126x SHARC Processor Hardware Reference
IMASK
registers determines whether a latched
DAI_IRPTL_FE
bit during chained DMA, programs
PCI
Bits Vector Interrupt
Address Name
14 0x38 SP1I
0 0x44 SP0I
15 0x3C SP3I
1 0x48 SP2I
16 0x40 SP5I
2 0x4C SP4I
14 0x38 SP1I
0 0x44 SP0I
15 0x3C SP3I
1 0x48 SP2I
16 0x40 SP5I
, ,
LIRPTL DAI_IRPTL_PRI
DMA Data Buffer
Channel
0 RXSP1A, TXSP1A
2 RXSP0A, TXSP0A
4 RXSP3A, TXSP3A
6 RXSP2A, TXSP2A
8 RXSP5A, TXSP5A
10 RXSP4A, TXSP4A
1 RXSP1B, TXSP1B
3 RXSP0B, TXSP0B
5 RXSP3B, TXSP3B
7 RXSP2B, TXSP2B
9 RXSP5B, TXSP5B
I/O Processor
,
7-5