Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 310

IOP/Core Interaction Options
When none of the peripherals request bus access, the highest priority
peripheral, for example, peripheral#0, is granted the bus. However, this
does not change the currently assigned priorities to various peripherals.
Within a peripheral group the priority is highest for the higher indexed
peripheral (see
highest priority.
Table 7-3. DMA Channel Allocation and Parameter Register
Assignments
DMA Data Buffer
Channel
Number
0 (highest pri- RXSP1A, TXSP1A
ority)
1 RXSP1B, TXSP1B
2 RXSP0A, TXSP0A
3 RXSP0B, TXSP0B
4 RXSP3A, TXSP3A
5 RXSP3B, TXSP3B
6 RXSP2A, TXSP2A
7 RXSP2B, TXSP2B
8 RXSP5A, TXSP5A
9 RXSP5B, TXSP5B
10 RXSP4A, TXSP4A
11 RXSP4B, TXSP4B
12 IDP_FIF0
13 IDP_FIF0
14 IDP_FIF0
15 IDP_FIF0
7-20
Table 7-3). For example in SP01 (group A), SP1 has the
Group
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
ADSP-2126x SHARC Processor Hardware Reference
IOP Address of Data
Buffers
0xC65, 0xC64
0xC67, 0xC66
0xC61, 0xC60
0xC63, 0xC62
0x465, 0x464
0x467, 0x466
0x461, 0x460
0x463, 0x462
0x865 or 0x864
0x867 or 0x866
0x861 or 0x860
0x863 or 0x862
0x24D0
0x24D0
0x24D0
0x24D0
Description
Serial Port 1A Data
Serial Port 1B Data
Serial Port 0A Data
Serial Port 0
B Data
Serial Port 3A Data
Serial Port 3B Data
Serial Port 2A Data
Serial Port 2B Data
Serial Port 5A Data
Serial Port 5B Data
Serial Port 4A Data
Serial Port 4B Data
DAI IDP Channel 0
DAI IDP Channel 1
DAI IDP Channel 2
DAI IDP Channel 3