Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 835

RXSP2B register, 9-46
RXSP3A register, 9-46
RXSP4A register, 9-48
RXSP4B register, 9-48
RXSP5A register, 9-48
RXSPI and TXSPI buffer registers,
RXSPI buffer, 10-3
RXSPI buffer receive data See RXSPI buffer
RXSPI register, 10-12, 10-37, 10-39,
10-42, A-101
RXSPI_SHADOW register,
RXSPxB register, 9-47, 9-48,
RXSPx registers, 7-23,
RXSR register, 10-2, 10-39,
S
SAMPLE instruction, 6-6
sampling edge, defined,
sampling receive data and frame syncs,
saturation (ALU saturation mode),
saturation maximum values,
saturation on store, G-9
scale (floating-point operation),
SCHEN_A and SCHEN_B bit,
SCKx pins, 10-4, 10-8,
SCLKx pins, 9-6
SDEN bit, 7-30, 9-55,
secondary processing element,
secondary registers, 1-8, 2-40, 4-4, 4-6,
for computational units (SRCU) bit,
2-41, A-5
for DAGs (SRDxH/L) bits,
for register file (SRRFH/L) bit,
secondary registers for DAGs (SRDxH/L)
bits, A-5
secondary registers for register file
(SRRFH/L) bit, A-5
2
selecting I S transmit and receive channel
order (FRFS), 9-16,
ADSP-2126x SHARC Processor Hardware Reference
10-33
A-101
9-50
A-85
A-100
10-5
9-36
G-9
2-26
2-17
A-77
10-26
A-77
2-45
A-5
A-5
A-5
9-21
selecting transmit and receive channel order
(FRFS), 9-16, 9-21
semaphores, G-9
SENDZ bit, 10-41
SENDZ (send zeros) bit,
sensing interrupts, 3-53
serial clock (SPORTx_CLK) pins,
Serial Data Routing Control SRU_DATx,
Group B) registers,
serial inputs, 11-3
serial modes, specifying,
serial peripheral interface clock See SPICLK
clock signal
serial peripheral interface See SPI port
serial port
chained DMA enable See SCHEN,
SPICHEN bits
clock, internal clock See ICLK, MSTR
2
(I S mode only) bits
connections, 9-5
controlling channel signal direction See
SPCTLx registers
controlling of See SPCTLx registers
controlling with See SPTRAN bit in
SPCTLx registers
control registers See SPCTLx registers
count See SPCNTx registers
data independent transmit/receive frame
sync See DITFS bit
data types, 9-41
DMA chaining, 9-73
DMA channels, 9-66,
DMA enable See SDEN, SPIEN bits
DMA parameter registers,
DXA error status See ROVF_A or
TUVF_A bit
DXB data buffer status See DXS_B bit
DXB error status See ROVF_B or
TUVF_B bit
enable bit See SPEN_x bits
Index
10-44
9-6
A-118
11-5
9-67
9-69
I-25