Frame Sync Output Synchronization With External Clock - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

• Pulse width. A 16-bit value that determines the width of the fram-
ing pulse. Settings for pulse width can be zero to
width is equal to zero, then the actual pulse width of the output
frame sync is:
For even divisors:
For odd divisors:
The frequency of the frame sync output is determined by:
Frequency of Frame Sync Output =
When the divisor is set to any value other than zero or one, the
ADSP-2126x operates in Normal mode.
The frame sync A divisor is specified in bits 19–0 of the
register and the frame sync B divisor is specified in bits 19–0 of the
register. The pulse width of frame sync output is equal to the
PCG_CTLB_0
number of input clock periods specified in the 16-bit field of the
register. Bits 15–0 specify the pulse width of frame sync A, and bits 31–16
specify the pulse width of frame sync B.
Frame Sync Output Synchronization with External
Clock
The frame sync output may be synchronized with an external clock by
programming the
priately. In this mode, the PCG frame sync output is synchronized with
the rising edge of the external clock (shown in
clock is routed to the PCG block from any of the SRU group E sources
ADSP-2126x SHARC Processor Hardware Reference
Frame Sync Divisor
Frame Sync Divisor – 1
Frequency of Clock Input
Frame Sync Divisor
,
SRU_EXT_MISCA SRU_CLK2
Precision Clock Generator
DIV-1
2
2
and
SRU_CLK3
Figure 13-2). The external
. If the pulse
PCG_CTLA_0
PCG_PW
registers appro-
13-5