Receive Multichannel Frame Sync Source; Active State Transmit Data Valid; Multichannel Status Bits - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

The 4-bit
MFD
( ,
SPMCTL01 SPMCTL23
sync pulse and the first data bit in multichannel mode. The value of
the number of serial clock cycles of the delay. Multichannel frame delay
allows the processor to work with different types of telephony interface
devices.
A value of zero for
first data bit. The maximum value allowed for
may occur before data from the last frame has been received, because
blocks of data occur back to back.

Receive Multichannel Frame Sync Source

Bit 14 (IMFS) in the
the serial port uses an internally generated frame sync (if set, =1) or frame
sync from an external (if cleared, =0) source.

Active State Transmit Data Valid

Bit 16 ( ) in the
LTDV
level of the transmit data valid signals (
(inverted) if set (=1) or active high if cleared (=0). These signals are actu-
ally
SPORT0_FS
multichannel operation. They indicate which timeslots have valid data to
transmit. Active high (0) is the default.

Multichannel Status Bits

Bit 29 ( ) in the
ROVF
mation. This bit indicates if the channel has received new data if set (=1)
or not if cleared (=0) while the
existing data.
Bits 31-30 (
RXS_A)
tus of the channel's receive buffer contents as follows: 00 = buffer empty,
01 = reserved, 10 = buffer partially full, 11 = buffer full.
ADSP-2126x SHARC Processor Hardware Reference
field (bits 4-1) in the Multichannel Control registers
, and
SPMCTL45
causes the frame sync to be concurrent with the
MFD
,
SPCTL1 SPCTL3
,
SPCTL0 SPCTL2
, and
SPORT2_FS SPORT4_FS
,
SPCTL1 SPCTL3
RXSPxA
in the
SPCTL1
) specifies a delay between the frame
is 15. A new frame sync
MFD
and registers selects whether
SPCTL5
and registers selects the logic
SPCTL4
,
TDV01 TDV23
reconfigured as outputs during
, registers provides status infor-
SPCTL5
buffer is full. New data overwrites
, , registers indicate the sta-
SPCTL3 SPCTL5
Serial Ports
MFD
, ) as active low
TDV45
9-29
is