Bypass As A Pass Through; Bypass Mode - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

If the pulse width is equal to zero, then the actual pulse width of the frame
sync output is equal to:
DIVISOR
2
if the divisor is even, or
DIVISOR – 1
2
if the divisor is odd.

Bypass Mode

When the divisor for the frame sync has a value of zero or one, the frame
sync is in Bypass mode, and the
than in Normal mode. Two bit fields determine the operation in this
mode. The One Shot Frame Sync A or B (
respectively) determines if the frame sync has the same width as the input,
or of a single strobe. These bits also determine whether the Active Low
Frame Sync Select for the Frame Sync A or B (
respectively) inverts the input. For additional information about the
register, see
PCG_PW

In Bypass mode, bits 15–2 and bits 31–18 of the
are ignored.

Bypass as a Pass Through

When the
STROBEA
in the
PCG_PW
output equals the input. If
unit B is set, then the signal is inverted.
Bypass mode also enables the generation of a strobe pulse ("one shot").
Strobe usage ignores the counter and looks to the SRU to provide the
input signal.
13-10
Figure A-60 on page
bit in the
PCG_PW
register for unit B equals zero, the unit is bypassed and the
INVFSA
ADSP-2126x SHARC Processor Hardware Reference
register has different functionality
PCG_PW
STROBEx
INVFSx
A-146.
register for unit A or the
(bit 1) for unit A or
) bit (bits 0 and 16,
) bit (bits 1 and 17,
register
PCG_PW
STROBEB
(bit 17) for
INVFSB
bit