Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 628

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Table of Contents

Core Registers

Table A-2. Mode Control 1 Register (MODE1) Bit Descriptions (Cont'd)

Nesting Multiple Interrupts Enable. Enables (nest if set, = 1) or dis-

ables (no nesting if cleared, = 0) interrupt nesting in the interrupt

controller. When interrupt nesting is disabled, a higher priority inter-

rupt can not interrupt a lower priority interrupt's service routine.

Other interrupts are latched as they occur, but the processor processes

them after the active routine finishes. When interrupt nesting is

enabled, a higher priority interrupt can interrupt a lower priority

interrupt's service routine. Lower interrupts are latched as they occur,

but the processor processes them after the nested routines finish.

Global Interrupt Enable. Enables (if set, = 1) or disables (if cleared,

= 0) all maskable interrupts.

ALU Saturation Select. Selects whether the computational units satu-

rate results on positive or negative fixed–point overflows (if 1) or

return unsaturated results (if 0).

Fixed–Point Sign Extension Select. Selects whether the computa-

tional units sign-extend short-word, 16-bit data (if 1) or zero-fill the

upper 32 bits (if 0).

Truncation Rounding Mode Select. Selects whether the computa-

tional units round results with round-to-zero (if 1) or round-to-near-

Rounding For 32-Bit Floating-Point Data Select. Selects whether the

computational units round floating-point data to 32 bits (if 1) or

round to 40 bits (if 0).

Processor Element Y Enable. Enables computations in PEy—SIMD

mode—(if 1) or disables PEy—SISD mode—(if 0).

When set, Processing Element Y (computation units and register files)

accepts instruction dispatches. When cleared, Processing

Element Y goes into a low power mode.

Note if SIMD Mode disabled you can load data to the secondary reg-

isters e.g. s0=dm(i0,m0); only computation does not work.

ADSP-2126x SHARC Processor Hardware Reference