Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 471

Table 10-3 provides the bit descriptions for the
Table 10-3. SPIBAUD Register Bits
Bit(s) Name
0
15:1 BAUDR
31:16 Reserved
Table 10-4 lists several possible baud rate values for the
Table 10-4. SPI Master Baud Rate Example
BAUDR Decimal Value
0
1
2
3
4
5
and up to 32,767 (0x7FFF)
1 BAUDR decimal values of 6 to 32,766 are also possible.
ADSP-2126x SHARC Processor Hardware Reference
Function
Reserved
Baud Rate enables the SPICLK baud rate per the following
equation:
SPI Baud Rate = Core clock (CCLK) divided by (4* BAUDR)
SPI Clock Divide Factor
N/A
4
8
12
16
20
1 131,068
Serial Peripheral Interface Port
SPIBAUD
Baud Rate for CCLK @ 200 MHz
N/A
50 MHz
25 MHz
16.67 MHz
12.5 MHz
10.0 MHz
1.526 kHz
register.
Default
0
register.
SPIBAUD
10-35