Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 482

Programming Model
3. Activate the desired slaves by clearing one or more of the SPI flag
bits (
SPIFLGx
4. For a single DMA, define the parameters of the DMA transfer by
writing to the
chaining, write the chain pointer address to the
Write to the SPI DMA configuration registers, (
DMA direction (
( , bit 0). If DMA chaining is desired, set (= 1) the
SPIDEN
4) in the
SPIDMACx
If DPI pins are used as slave selects, programs should route them appro-
priately after the
before enabling the DMA. When
are automatically activated by the SPI ports.
When enabled as a master, the DMA engine transmits or receives data as
follows.
1. If the SPI system is configured for transmitting, the DMA engine
reads data from memory into the SPI DMA FIFO. Data from the
DMA FIFO is loaded into the
transmit shift register. This initiates the transfer on the SPI port.
2. If configured to receive, data from the
cally loaded into the SPI DMA FIFO. Then the DMA engine reads
data from the SPI DMA FIFO and writes to memory. Finally, the
SPI initiates the receive transfer.
3. The SPI generates the programmed signal pulses on
data is shifted out of
4. The SPI continues sending or receiving words until the SPI DMA
word count register transitions from 1 to 0.
If the DMA engine is unable to keep up with the transmit stream during a
transmit operation because the IOP requires the IOD (I/O data) bus to
10-46
) of the
SPIFLGx
,
IISPIx IMSPIx
, bit 1) and to enable the SPI DMA engine
SPIRCV
registers.
and
SPICTLx SPIBAUDx
CPHASE
and in from
MOSI
ADSP-2126x SHARC Processor Hardware Reference
registers, if
CPHASE
, and registers. For DMA
CSPIx
SPIDMACx
registers are configured, but
= 0, or
CPHASE
registers and then into the
TXSPIx
registers is automati-
RXSPIx
simultaneously.
MISO
= 1.
registers.
CPSPIx
), to specify the
bit (bit
SPICHEN
= 1, the DPI pins
and the
SPICLK