Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 494

Serial Inputs
protocol is designed to receive audio channels in I
Pair, or Right-justified mode. One frame sync cycle indicates one 64-bit
left-right pair, but data is sent to the FIFO as 32-bit words (that is,
one-half a frame at a time).
Contained within the 32-bit word is an audio signal that is normally 24
bits wide. An additional four bits are available for status and formatting
data (compliant with the IEC 90958, S/PDIF, and AES3 standards). An
additional bit identifies the left-right one-half of the frame. If the data is
not in IEC standard format, the serial data can be any data word up to 28
bits wide. Regardless of mode, bit 3 always specifies if the data is received
in the first half (left channel), or the second half (right channel) of the
same frame, as shown in
encode one of the eight channels being passed through the FIFO to the
core. The FIFO output may feed eight DMA channels, where the appro-
priate DMA channel (corresponding to the channel number) is selected
automatically.
AUDIO DATA (24 BITS)
31
Figure 11-3. Word Format

Note that each input channel has its own clock and frame sync
input, so unused IDP channels do not produce data and therefore
have no impact on FIFO throughput. The clock and frame sync of
any unused input should be assigned to
acquisition.
The framing format is selected by using
channel) in the
control the input format modes for each of the eight channels. The eight
groups of three bits indicate the mode of the serial input for each of the
eight IDP channels, as shown in
11-4
Figure 11-3. The remaining three bits are used to
register. The bits
IDP_CTL
Table
ADSP-2126x SHARC Processor Hardware Reference
2
S, Left-justified Sample
AUDIO STREAM
L/R
STATUS
8 7
4
to avoid unintentional
LOW
bits (three bits per
IDP_SMODEx
of the
[31:8] IDP_CTL
11-1.
IDP
CHNL
3 2 0
register