Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 627

Table A-2. Mode Control 1 Register (MODE1) Bit Descriptions
Bit Name
0 BR8
1 BR0
2 SRCU
3 SRD1H
4 SRD1L
5 SRD2H
6 SRD2L
7 SRRFH
9–8 Reserved
10 SRRFL
ADSP-2126x SHARC Processor Hardware Reference
Description
Bit-Reverse Addressing For Index I8 Enable. Enables (bit reversed if
set, = 1) or disables (normal if cleared, = 0) bit-reversed addressing for
accesses that are indexed with DAG2 register I8.
Bit-Reverse Addressing For Index I0 Enable. Enables (bit reversed if
set, = 1) or disables (normal if cleared, = 0) bit-reversed addressing for
accesses that are indexed with DAG1 register I0.
MRx Result Registers Swap Enable. Enables the swapping of the
MRF and MRB registers contents if set (= 1). This can be used as
foreground and background registers. In SIMD Mode the swapping
also performed between MSF and MSB registers.
This works similar to the RF swapping instructions Rx<->Sx.
Secondary Registers For DAG1 High Enable. Enables (use secondary
if set, = 1) or disables (use primary if cleared, = 0) secondary DAG1
registers for the upper half (I, M, L, B7–4) of the address generator.
Secondary Registers For DAG1 Low Enable. Enables (use secondary
if set, = 1) or disables (use primary if cleared, = 0) secondary DAG1
registers for the lower half (I, M, L, B3–0) of the address generator.
Secondary Registers For DAG2 High Enable. Enables (use secondary
if set, = 1) or disables (use primary if cleared, = 0) secondary DAG2
registers for the upper half (I, M, L, B15–12) of the address generator.
Secondary Registers For DAG2 Low Enable. Enables (use secondary
if set, = 1) or disables (use primary if cleared, = 0) secondary DAG2
registers for the lower half (I, M, L, B11–8) of the address generator.
Secondary Registers For Register File High Enable. Enables (use sec-
ondary if set, = 1) or disables (use primary if cleared, = 0) secondary
data registers for the upper half (R15-R8/S15-S8) of the computa-
tional units.
Secondary Registers For Register File Low Enable. Enables (use sec-
ondary if set, = 1) or disables (use primary if cleared, = 0) secondary
data registers for the lower half (R7-R0/S7-S0) of the computational
units.
Registers Reference
A-5