Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 299

parameters to the index, modify, and count registers, then set the DMA
enable bit to re-enable DMA.
Chained DMA. Chained DMA sequences are a set of multiple DMA
operations, each autoinitializing the next in line. To start a new DMA
sequence after the current one is finished, the IOP automatically loads
new index, modify, and count values from an internal memory location
pointed to by that channel's chain pointer (
programs can set up consecutive DMA operations and each operation can
have different attributes.

Chaining is only supported on the SPI and SPORT DMA chan-
nels. The parallel port, and IDP port do not support chaining.
In general, a DMA sequence starts when one of the following occurs:
• Chaining is disabled, and the DMA enable bit transitions from low
to high.
• Chaining is enabled, DMA is enabled, and the chain pointer regis-
ter address field is written with a nonzero value. In this case, TCB
chain loading of the channel parameter registers occurs first.
• Chaining is enabled, the chain pointer register address field is non-
zero, and the current DMA sequence finishes. Again, TCB chain
loading occurs.
A DMA sequence ends when one of the following occurs:
• The count register decrements to zero, and the
• Chaining is disabled and the channel's DMA enable bit transitions
from high to low. If the DMA enable bit goes low (=0) and chain-
ing is enabled, the channel enters chain insertion mode and the
DMA sequence continues.
TCB in an Active Chain" on page 7-16.
ADSP-2126x SHARC Processor Hardware Reference
) register. Using chaining,
CP
For more information, see "Inserting a
I/O Processor
register is zero.
CP
7-9