Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 697

SPCTL0 (0xc00)
SPCTL2 (0x400)
SPCTL4 (0x800)
31 30 29 28 27 26
TXS_A
Data Buffer Channel A Status
11=Full 10=Partially Full 00=Empty
TUVF_A
Channel A Underflow Status (sticky)
TXS_B
Data Buffer Channel B Status
11=Full 10=Partially Full 00=Empty
TUVF_B
Channel B Underflow Status (sticky)
Reserved
BHD
Buffer Hang Disable
1=Ignore Core Hang
0=Core Stall when TXn Full or RXn Empty
Reserved
SCHEN_B
SPORT Transmit DMA Channel B
Chaining Enable
1=Enable
0=Disable
Reserved
CKRE
Active Clock Edge for Data and Frame
Sync Driving
1=Rising Edge
0=Falling Edge
OPMODE
SPORT Operation Mode
1=I2S or Left-justified Sample pair Mode
0=DSP Serial Mode/Multichannel Mode
Reserved
PACK
16/32 Packing
1=Packing
0=No Packing
Figure A-23. SPCTLx Transmit Control Bits – Multichannel Mode
ADSP-2126x SHARC Processor Hardware Reference
25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
Registers Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
LTDV
Active Low MC Transmit
Data valid
1=Active low FS
0=Active High FS
Reserved
SDEN_A
SPORT Transmit DMA
Channel A Enable
1=Enable
0=Disable
SCHEN_A
SPORT Transmit DMA
Channel A Chaining
Enable
1=Enable
0=Disable
SDEN_B
SPORT Transmit DMA
Channel B Enable
1=Enable
0=Disable
Reserved
DTYPE
Data Type
00=Right Justify, Fill MSB
with 0's
01=Right Justify, Sign
extend MSB
10=Compand µ-law
11=Compand A-law
LSBF
Serial Word Bit Order
1=LSB First
0=MSB First
SLEN
Serial Word Length-1
A-75