Memory Organization Enhancements; Parallel Port Enhancements; I/O Architecture Enhancements; Instruction Set Enhancements - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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Table of Contents

Differences From Previous SHARCs

Memory Organization Enhancements

The ADSP-2126x memory map differs from that of the ADSP-2106x

DSPs. The system memory map supports double-word transfers each

cycle, reflects extended internal memory capacity for derivative designs,

and works with an updated control register for SIMD support. The

ADSP-2126x family provides enough on-chip memory for several audio

The parallel port differs from that of the ADSP-2106x DSPs. A new pack-

ing mode permits DMA for instructions and data to and from 8-bit

external memory. The parallel port supports SRAM, EPROM, and flash

memory. There are two modes supported for transfers. In one mode, 8-bit

data and 8-bit address can be transferred. In another mode, data and

address lines are multiplexed to transfer 16 bits of address/data.

The I/O processor on the ADSP-2126x provides much greater throughput

than that on the ADSP-2106x DSPs.

The ADSP-2126x DMA controller supports up to 22 channels compared

to 14 channels on the ADSP-21161 processor. DMA transfers occur at

clock speed in parallel with full speed processor execution.

The ADSP-2126x provides source code compatibility with the previous

SHARC processor family members, to the application assembly source

code level. All instructions, control registers, and system resources avail-

able in the ADSP-2106x core programming model are also available in the

ADSP-2126x SHARC Processor Hardware Reference