Packing Mode 11 - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

MODE 11
1x20-bit
31
MODE 10
2x16-bit
31
MODE 01
tri-word
C
31
MODE 00
4x8-bit
D
31
Figure 11-7. Packing Modes in IDP_PDAP_CTL

Packing Mode 11

Mode 11 provides for 20 bits coming into the packing unit and 32 bits
going out to the FIFO in a single cycle. On every clock edge, 20 bits of
data are moved and placed in a 32-bit register, left-aligned. That is, bit 19
maps to bit 31. The lower bits [11:0] are always set to zero, as shown in
Figure 11-7 on page
This mode sends one 32-bit word to FIFO for each input clock cycle—the
DMA transfer rate will match the PDAP input clock rate.
Packing Mode 10
On the first clock edge (cycle A), the packing unit latches parallel data up
to 16 bits wide (bits 19–4 of the parallel input) and places it in bits 15–0
(the lower half of the word), then waits for the second clock edge (cycle
B). On the second clock edge (cycle B), the packing unit takes the same
set of inputs and places the word into bits 31–16 (the upper half of the
word).
ADSP-2126x SHARC Processor Hardware Reference
A
B
16 15
B
21 20
C
24 23 16 15
11-9.
RESERVED
12 11
A
A
10 9
B A
8 7
Input Data Port
0
0
0
0
11-9