Alternate (Secondary) Dag Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Setting DAG Modes
register load operation on both processing elements with register load
broadcasting enabled. In
tary data registers. Note also that the letters a and b (as in Ma or Mb)
indicate numbers for modify registers in DAG1 and DAG2. The letter a
indicates a DAG1 register and can be replaced with 0 through 7. The let-
ter b indicates a DAG2 register and can be replaced with 8 through 15.

The
PEYEN
cast operations. Broadcast loading is particularly useful in SIMD
applications where the algorithm needs identical data loaded into
each processing element. For more information on SIMD mode (in
particular, a list of complementary data registers), see
(Computational) Operations" on page
Table 4-1. Dual Processing Element Register Load Broadcasts
Instruction syntax
PEx explicit operations
PEy implicit operations

Alternate (Secondary) DAG Registers

To facilitate fast context switching, the DSP includes alternate register sets
for all DAG registers. Bits in the
isters become accessible. While inaccessible, the contents of alternate
registers are not affected by DSP operations. Note that there is a maxi-
mum one cycle latency between writing to
an alternate register set. The alternate register sets for the DAGs are
described in this section. For more information on alternate data and
results registers, see
4-6
Table 4-1, note that
bit (SISD/SIMD mode select) does not influence broad-
Rx = DM(I1,Ma); {Syntax #1}
Rx = PM(I9,Mb); {Syntax #2}
Rx = DM(I1,Ma), Rx = PM(I9,Mb); {Syntax #3}
Rx = DM(I1,Ma); {Explicit #1}
Rx = PM(I9,Mb); {Explicit #2}
Rx = DM(I1,Ma), Rx = PM(I9,Mb); {Explicit #3}
Sx = DM(I1,Ma); {Implicit #1}
Sx = PM(I9,Mb); {Implicit #2}
Sx = DM(I1,Ma), Sx = PM(I9,Mb); {Implicit #3}
MODE1
"Alternate (Secondary) Data Registers" on page
ADSP-2126x SHARC Processor Hardware Reference
and are complemen-
Rx Sx
2-50.
register control when alternate reg-
and being able to access
MODE1
"SIMD
2-40.