Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 692

I/O Processor Registers
SPCTL0 (0xc00)
SPCTL1 (0xc01)
SPCTL2 (0x400)
SPCTL3 (0x401)
SPCTL4 (0x800)
SPCTL5 (0x800)
(Bits 31–16)
DXS_A
Data Buffer Channel A Status
11=Full 10=Partially Full 00=Empty
DERR_A
Channel A Error Status (sticky)
SPTRAN=1, Transmit Under-
flow Status, SPTRAN=0
Receive Overflow Status
DXS_B
Data Buffer Channel B Status
11=Full 10=Partially Full 00=Empty
DERR_B
Channel B Error Status (sticky)
SPTRAN=1 Transmit Underflow Status
SPTRAN=0 Receive Overflow Status
SPTRAN
SPORT Data Direction
1=Transmit
0=Receive
SPEN_B
SPORT Enable B
1=Enable
0=Disable
BHD
Buffer Hang Disable
1=Ignore Core Hang
0=Core Stall when TXSPx full or RXSPx Empty
Figure A-18. SPCTLx Control Bits for Standard DSP Serial Mode
(Upper)
A-70
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
0 1 0 0 0 0 0 0
LFS
Active Low Frame Sync
1=Active Low
0=Active High
LAFS
Late Frame Sync
1=Late Frame Sync
0=Early Frame Sync
SDEN_A
DMA Channel A Enable
1=Enable
0=Disable
SCHEN_A
DMA Channel A
Chaining Enable
1=Enable
0=Disable
SDEN_B
DMA Channel B Enable
1=Enable
0=Disable
SCHEN_B
DMA Channel B
Chaining Enable
1=Enable
0=Disable
FS_BOTH
Frame Sync Both
1=Issue Word Select if data is
present in both TXSPxy and
RXSPxy
0=Issue Word Select if data is
present in either of TXSPxy or
RXSPxy buffers