Transfer Protocol - Analog Devices ADSP-21261 SHARC Hardware Reference Manual


Table 8-2
data reads and writes.
Table 8-2. Unpacking Sequence for 32-Bit Data
Transfer
First
Second
Third
Fourth

Parallel port DMAs can only be performed to 32-bit (normal word)
internal memory.

Transfer Protocol

The external interface follows the standard asynchronous SRAM access
protocol. The programmable Data Cycle Duration (
Bus Hold Cycle (
to interface with memories having different access time requirements. The
data cycle duration is programmed via the
The hold cycle at the end of the data cycle is programmed via the
bit in the
PPCTL

Disabling the parallel port (
port FIFOs,
For standard asynchronous SRAM there are two transfer modes—8-bit
and 16-bit mode. In 8-bit mode, the address range is 0x0 to 0xFFFFFF
which is 16M bytes (4M 32-bit words). In 16-bit mode, the address range
is 0x0 to 0xFFFF which is a 128K bytes (32K 32-bit words). Although
programs can initiate reads or writes on one and two byte boundaries, the
parallel port always transfers 4 bytes (two 16-bit or four 8-bit words).
8-8
does not show
ALE
AD7–0, 32-bit to 8-bit
(8-bit bus, LSW first)
Word 1; bits 7–0
Word 1; bits 15–8
Word 1; bits 23–16
Word 1; bits 31–24
) addition at the end of each data cycle are provided
BHC
register.
, and
RXPP TXPP
ADSP-2126x SHARC Processor Hardware Reference
cycles; it shows only the order of the
AD15–0, 32-bit to 16-bit
(16-bit bus, LSW first)
Word 1; bits 15–0
Word 1; bits 31–16
bit in the
PPDUR
bit is cleared) flushes both parallel
PPEN
.
) and optional
PPDUR
register.
PPCTL
PPBHC