Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 185

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DAGs: the lower half of DAG1 (

), the lower half of DAG2 (

nate register sets.

MODE1 SELECT BIT

Figure 4-2. Data Address Generator Primary and Alternate Registers

To share data between contexts, a program places the data to be shared in

one half of either the current DAGs' registers or the other DAG's registers

and activates the alternate register set of the other half. The following

example demonstrates how code handles the maximum one cycle of

latency from the instruction that sets the bit in

ADSP-2126x SHARC Processor Hardware Reference

DAG1 REGISTERS (DATA MEMORY)

DAG2 REGISTERS (PROGRAM MEMORY)

Data Address Generators

), the upper half of DAG1

shows the DAGs' primary and alter-

), and the upper half

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