Masking Interrupts - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Interrupts and Sequencing
Table A-3 on page A-8
The DSP accepts external interrupts that are asynchronous to the DSP's
core clock (
CLCK
time. An external interrupt must be held low at least one
guarantee that the DSP samples the signal.

External interrupts must meet the setup and hold time require-
ments relative to the rising edge of
interrupt signal timing requirements, see the appropriate
ADSP-2126x data sheet.

Masking Interrupts

The sequencer supports interrupt masking—latching an interrupt, but not
responding to it. Except for the
maskable. If a masked interrupt is latched, the DSP responds to the
latched interrupt if it is later unmasked.
Interrupts can be masked globally or selectively. Bits in the
and registers control interrupt masking as shown in
LIRPTL
page A-3.
Table A-2 on page A-5
page A-27 lists all of the bits in
all of the bits in
All interrupts are masked at reset except for the non-maskable and boot
interrupts. For booting, the DSP automatically unmasks and uses the par-
allel port interrupt (
reset. Usage depends on whether the ADSP-2126x is booting from
EPROM, or an SPI master or slave. See also
page 12-28 for a description of DAI interrupts.
3-54
lists all of the bits in the
), allowing external interrupt signals to change at any
RESET
lists all of the bits in
IMASK
.
LIRPTL
) or high priority SPI port (
PPI
ADSP-2126x SHARC Processor Hardware Reference
register.
MODE2
/2. For information on
CCLK
and interrupts, all interrupts are
EMU
, Table A-8 on
MODE1
, and Table A-10 on page A-32
SPIHI
"DAI Interrupts" on
/2 cycle to
CCLK
, ,
MODE1 IMASK
Table A-1 on
lists
) interrupt after