Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 318

Setting Up DMA Parameter Registers

If the I/O processor modifies the index register past the maximum
19-bit value to indicate an address out of internal memory, the
index wraps around to zero. With the offset for the ADSP-2126x
processor, the wraparound address is 0x0008 0000.

If a program loads the count register with zero, the I/O processor
does not disable DMA transfers on that channel. The I/O proces-
sor interprets the zero as a request for 2
occurs because the I/O processor starts the first transfer before test-
ing the count value. The only way to disable a DMA channel is to
clear its DMA enable bit.

If a DMA channel is disabled, the I/O processor does not service
requests for that channel, whether or not the channel has data to
transfer.
The processor's 22 DMA channels are numbered as shown in
This table also shows the control, parameter, and data buffer registers that
correspond to each channel.

In SP01, SP1 has a higher priority. Similarly, for SP23 and SP45,
the odd numbered SPs have a higher priority (SP3, SP5).
Table 7-5. DMA Channel Registers: Controls, Parameters
and Buffers
DMA Control
Channel Registers
Number
0 SPCTL1
1 SPCTL1
2 SPCTL0
3 SPCTL0
7-28
Parameter Registers
IISP1A, IMSP1A,
CSP1A, CPSP1A
IISP1B, IMSP1B,
CSP1B, CPSP1B
IISP0A, IMSP0A,
CSP0A, CPSP0A
IISP0B, IMSP0B,
CSP0B, CPSP0B
ADSP-2126x SHARC Processor Hardware Reference
16
transfers. This count
Buffer Registers Description
RXSP1A, TXSP1A Serial Port 1A Data
RXSP1B, TXSP1B Serial Port 1B Data
RXSP0A, TXSP0A Serial Port 0A Data
RXSP0B, TXSP0B Serial Port 0B Data
Table 7-5.