Core Stalls - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Stalls

Like all previous SHARC processors, there are a number of conditions
that cause the core to temporarily stop fetching and executing further
instructions. This event, known as a core stall, occurs when an instruction
accesses a peripheral's data-buffer. Specifically, the core stalls when it
reads an empty receive buffer or writes a full transmit buffer. Execution
resumes once the peripheral moves a valid word of data into the receive
buffer or when the peripheral sends one word out from the transmit
buffer.
In addition to standard core stall situations, there are four other condi-
tions that cause the ADSP-2126x core to stall. The following instructions
or sequences of instructions will cause the processor core to stall for one or
more cycles. These stalls were introduced to facilitate the doubling of the
core clock rate without modifying the 3-deep instruction-pipeline.
1. Reading or writing any memory mapped register in a conditional
instruction stalls the core for one cycle. This means that a total of
two cycles are needed for that instruction to complete.
2. Reading the System/Emulator memory-mapped registers shown in
Table 3-7
two cycles are needed for that instruction.
ADSP-2126x SHARC Processor Hardware Reference
stalls the processor for one cycle. Therefore, a total of
Program Sequencer
3-21