Restrictions On Mixing 32-Bit Words And 48-Bit Words - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

ADSP-2126x Memory Map

Restrictions on Mixing 32-Bit Words and 48-Bit Words

There are some restrictions that stem from the memory column rotations
for three-column data (48- or 40-bit words) and they relate to the way
that three-column data can mix with four-column data (32-bit words) in
memory. These restrictions apply to mixing 48- and 32-bit words, because
the DSP uses a normal word address to access both of these types of data
even though 48-bit data maps onto three columns of memory and 32-bit
data maps onto two columns of memory.
When a system has a range of three-column (48-bit) words followed by a
range of two-column (32-bit) words, there is often a gap of empty 16-bit
locations between the two address ranges. The size of the address gap var-
ies with the ending address of the range of 48-bit words. Because the
addresses within the gap alias to both 48- and 32-bit words, a 48-bit write
into the gap corrupts 32-bit locations, and a 32-bit write into the gap cor-
rupts 48-bit locations. The locations within the gap are only accessible
with short word (16-bit) accesses.
Calculating the starting address for four column data that minimizes the
gap after three column data is useful for programs that are mixing three
and four column data. Given the last address of the three column (48-bit)
data, the starting address of the 32-bit range that most efficiently uses
memory can be determined by the equation shown in
Listing 5-2. Starting Address
m = B + 2 [(n MOD K) – TRUNC (n MOD K) / 4)]
where:
• K is 21844 for RAM and 43690 for ROM
• n is the number of contiguous 48-bit words allocated in the inter-
nal memory block (n < 43,690 for ROM, n < 21844 for RAM)
5-16 ADSP-2126x SHARC Processor Hardware Reference
Listing 5-2.