Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 671

Table A-16. BRKCTL Register Bit Descriptions (Cont'd)
Bit # Name
5–4 DA2MODE
7–6 IO1MODE
9–8 Reserved
10 NEGPA1
11 NEGDA1
12 NEGDA2
13 NEGIA1
14 NEGIA2
15 NEGIA3
16 NEGIA4
17 NEGIO1
18 Reserved
ADSP-2126x SHARC Processor Hardware Reference
Function
DA2 Triggering Mode
00 = Breakpoint Disabled
01 = WRITE Access
10 = READ Access
11 = Any Access
IO1 Triggering Mode trigger on the following conditions:
Mode Triggering condition
00 = Breakpoint is disabled
01 = WRITE accesses only
10 = READ accesses only
11 = Any access
Negate Program Memory Data Address Breakpoint
Enable breakpoint events if the address is greater than the end
register value OR less than the start register value. This function
is useful to detect index range violations in user code.
0 = Disable Breakpoint
1 = Enable Breakpoint
Negate Data Memory Address Breakpoint #1
For more information, see NEGPA1 bit description.
Negate Data Memory Address Breakpoint #2
For more information, see NEGPA1 bit description.
Negate Instruction Address Breakpoint #1
0 = Disable Breakpoint
1 = Enable Breakpoint
Negate Instruction Address Breakpoint #2
For more information, see NEGPA1 bit description.
Negate Instruction Address Breakpoint #3
For more information, see NEGPA1 bit description.
Negate Instruction Address Breakpoint #4
For more information, see NEGPA1 bit description.
Negate I/O Address Breakpoint
For more information, see NEGPA1 bit description.
Registers Reference
A-49