Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 161

this table are spaced at 4-instruction intervals. Each interrupt vector has
associated latch and mask bits. For a list of interrupt vector addresses and
their associated latch and mask bits, see
"Interrupt Register (LIRPTL)" on page
(IMASK)" on page
page A-25 lists the latch and mask bits.
To process an interrupt, the DSP's program sequencer:
1. outputs the appropriate interrupt vector address.
2. pushes the current PC value (the return address) onto the PC stack.
3. pushes the current value of the
the status stack (if the interrupt is
4. resets the appropriate bit in the interrupt latch register (
LIRPTL
5. alters the interrupt mask pointer bits (
interrupt nesting state, depending on the nesting mode.
At the end of the interrupt service routine (ISR), the sequencer processes
the return-from-interrupt (
below. Between servicing and returning, the sequencer clears the latch bit
of the in-progress ISR every cycle until the
the same interrupt from recurring until the ISR is done. Refer to the
( ) code example
CI
1. Returns to the address stored at the top of the PC stack.
2. Pops this value off the PC stack.
3. Pops the status stack (if the
were pushed for the
4. Clears the appropriate bit in the interrupt mask pointer (
ADSP-2126x SHARC Processor Hardware Reference
A-25, and "Interrupt Latch Register (IRPTL)" on
registers).
) instruction and performs the steps shown
RTI
on page 3-60 to learn how to prevent this clearing.
IRQ2–0
Program Sequencer
Table B-2 on page
A-30, "Interrupt Mask Register
and
ASTATx/y
, or timer).
IRQ2–0
) to reflect the current
IMASKP
is executed. This prevents
RTI
and
ASTATx,y MODE1
, or timer interrupt).
B-2.
registers onto
MODE1
and
IRPTL
JUMP
status registers
IMASKP
3-49
).