Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 71

• The DSP does not provide inexact flags. An inexact flag is an
exception flag whose bit position is inexact. The inexact exception
occurs if the rounded result of an operation is not identical to the
exact (infinitely precise) result. Thus, an inexact exception always
occurs when an overflow or an underflow occurs.
• NAN (Not-A-Number) inputs generate an invalid exception and
return a quiet NAN (all 1s).
• Denormal operands, using denormalized (or tiny) numbers, flush
to zero when input to a computational unit and do not generate an
underflow exception. A denormal operand is one of the float-
ing-point operands with an absolute value too small to represent
with full precision in the significant. The denormal exception
occurs if one or more of the operands is a denormal number. This
exception is never regarded as an error.
• The processor supports round-to-nearest and round-toward-zero
modes, but does not support round-to-+Infinity and round-to
--Infinity.
IEEE single-precision floating-point data uses a 23-bit mantissa with an
8-bit exponent plus sign bit. In this case, the computation unit sets the
eight LSBs of floating-point inputs to zeros before performing the opera-
tion. The mantissa of a result rounds to 23 bits (not including the hidden
bit), and the 8 LSBs of the 40-bit result clear to zeros to form a 32-bit
number, which is equivalent to the IEEE standard result.
In fixed-point to floating-point conversion, the rounding boundary is
always 40 bits, even if the
ADSP-2126x SHARC Processor Hardware Reference
bit is set.
RND32
Processing Elements
2-13