Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 23

SYSTEM DESIGN
Pin Descriptions ......................................................................... 15-2
Pin Multiplexing ................................................................... 15-2
Input Synchronization Delay ................................................. 15-4
Clock Derivation ................................................................... 15-4
Power Management Control Register ................................. 15-5
RESET and CLKIN .............................................................. 15-7
Reset Generators ................................................................... 15-9
Interrupt and Peripheral Timer Pins ..................................... 15-12
Core-Based Flag Pins ........................................................... 15-12
JTAG Interface Pins ............................................................ 15-12
Phase-Locked Loop Startup ................................................. 15-13
Conditioning Input Signals ....................................................... 15-14
Input Pin Hysteresis ............................................................ 15-14
Designing for High Frequency Operation .................................. 15-15
Clock Specifications and Jitter ............................................. 15-15
Other Recommendations and Suggestions ............................ 15-16
Decoupling Capacitors and Ground Planes .......................... 15-17
Oscilloscope Probes ............................................................. 15-17
Recommended Reading ....................................................... 15-18
Booting .................................................................................... 15-19
Parallel Port Booting ............................................................ 15-21
ADSP-2126x SHARC Processor Hardware Reference
Contents
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