Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 213

All transfers between the
are 40-bit transfers. The most significant 40 bits are transferred as shown
in Figure 5-3 on page
Figure 5-5 shows the transfer size between
the PM or DM data bus when using the long word (
Instruction Example
Figure 5-5. PX Register-to-Memory Transfers on PM Data Bus
The notation in
LW
ter-to-internal memory transfers over the PM or DM data bus for the
combined register. The
PX
(three column) transfers on bits 63-16 of the PM or DM data bus, unless
forced to be 64-bit (four column) transfers with the
mnemonic.
There is no implicit move when the combined
mode. For example, in SIMD mode, the following moves occur:
ADSP-2126x SHARC Processor Hardware Reference
register and data registers (
PX
5-7.
PX = PM (0x80000)LW;
DM (LW) or PM (LW)
Data Bus Transfer
64 bits
63 31
64 bits
63 31
Combined PX
Figure 5-5 shows an important feature of
register transfers to memory are 48-bit
PX
R0–R15
and internal memory over
PX
) option.
LW
0
0
(long word)
LW
register is used in SIMD
PX
Memory
or )
S0–S15
regis-
PX
5-9