Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 515

Listing 11-1. Interrupt-Driven Data Transfer
/* Using Interrupt-Driven Transfers from the IDP FIFO */
#define IDP_ENABLE
#define IDP_CTL
#define IDP_FIFO_GTN_INT (8)
#define IDP_FIFO
#define DAI_IRPTL_FE
#define DAI_IRPTL_RE
#define DAI_IRPTL_PRI (0x2484)
.section/dm seg_dmda;
.var OutBuffer[6];
.section/pm seg_pmco;
initIDP:
r0 = dm(IDP_CTL);
r0 = BSET r0 BY IDP_ENABLE;
dm(IDP_CTL) = r0;
r0 = BCLR r0 BY IDP_ENABLE;
r0 = BCLR r0 BY 10;
r0 = BCLR r0 BY 9;
r0 = BCLR r0 BY 8;
dm(IDP_CTL) = r0;
/*************************************************/
/* Connect the clock, data and frame sync of IDP */
/* channel 0 to DAI pin buffers 10, 11 and 12.
/*************************************************/
/* Connect IDP0_CLK_I to DAI_PB10_O
ADSP-2126x SHARC Processor Hardware Reference
(8) /* IDP_ENABLE = IDP_CTL[7] */
(0x24B0) /* Memory-mapped register */
/* Bit 8 in interrupt regs */
(0x24D0) /* IDP FIFO packing mode */
(0x2480) /* Falling edge int latch */
(0x2481) /* Rising edge int latch */
/* Interrupt priority */
/* Reset the IDP */
/* Set IDP serial input channel 0 */
/* to receive in I2S format
Input Data Port
*/
*/
*/
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