Group D Connections - Pin Signal Assignments - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Group D Connections – Pin Signal Assignments
Group D is used to specify any signals that will be driven off-chip by the
pin buffers. A pin buffer input (
the processor when the pin buffer enable is set (= 1). Note that DAI pins
19 and 20 may be configured as either active high or active low by setting
the corresponding invert bit.
Each physical pin (connected to a bonded pad) may be routed via the SRU
to any of the outputs of the DAI audio peripherals, based on the 6-bit val-
ues listed in Table
control the pins in other ways. These signals may be configured for use as
flags, timers, precision clock generators, or miscellaneous control signals.
Group D registers are
page A-127 through
ADSP-2126x SHARC Processor Hardware Reference
DAI_PBxx_I
12-5. The SRU also may be used to route signals that
, described in
SRU_PIN0-3
Figure A-49 on page
Digital Audio Interface
) is driven as an output from
Figure A-46 on
A-128.
12-21