Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 677

The address ranges of the emulation Breakpoint registers are negated by
setting the appropriate negation bits in the
information, see the
abled by setting the start address larger than the end address.
Four of the breakpoints monitor the instruction address. Two monitor the
data memory address. One monitors the program memory data address,
and one monitors the I/O address bus.
The instruction address breakpoints monitor the address of the instruc-
tion being executed, not the address of the instruction being fetched. If
the current execution is aborted, the breakpoint signal does not occur even
if the address is in range. Data address breakpoints (DA and PA only) are
also ignored during aborted instructions. The nine breakpoint sets appear
in Table A-18.
Table A-18. PSx, DMx, IOx, and EPx (Breakpoint) Registers
Register
PSA1S
PSA1E
PSA2S
PSA2E
PSA3S
PSA3E
PSA4S
PSA4E
DMA1S
DMA1E
DMA2S
DMA2E
ADSP-2126x SHARC Processor Hardware Reference
bit description. Each breakpoint can be dis-
NEGPA1
Function
Instruction Address Start #1
Instruction Address End #1
Instruction Address Start #2
Instruction Address End #2
Instruction Address Start #3
Instruction Address End #3
Instruction Address Start #4
Instruction Address End #4
Data Address Start #1
Data Address End #1
Data Address Start #2
Data Address End #2
Registers Reference
register. For more
EMUCTL
1
Group
IA
IA
IA
IA
IA
IA
IA
IA
DA
DA
DA
DA
A-55