Sport Interrupts - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPORT Control Registers and Data Buffers
can initiate periodic transfers. The counting of serial clock cycles applies
to internally- or externally-generated serial clocks.
The formula for the number of cycles between frame sync pulses is:
# of serial clocks between frame syncs = FSDIV + 1
Use the following equation to determine the value of
serial clock frequency and desired frame sync frequency:
The frame sync is continuously active when
should not be less than the serial word length minus one (the value of the
field in the Serial Port Control register), as this may cause an external
SLEN
device to abort the current operation or cause other unpredictable results.
If the serial port is not being used, the
counter for dividing an external clock or for generating a periodic pulse or
periodic interrupt. The serial port must be enabled for this mode of oper-
ation to work properly.
Exercise caution when operating with externally-generated transmit clocks
near the frequency of one-quarter of the processor's internal clock. There
is a delay between when the clock arrives at the
when data is output. This delay may limit the receiver's speed of opera-
tion. Refer to the data sheet for exact timing specifications.
Externally-generated late transmit frame syncs also experience a delay
from when they arrive to when data is output. This can also limit the max-
imum serial clock speed. Refer to the product-specific data sheet for exact
timing specifications.

SPORT Interrupts

Each serial port has an interrupt associated with it. For each SPORT, both
the A and B channel transmit and receive data buffers share the same
9-64
f
SPORTx_CLK
FSDIV =
f
SPORTx_FS
ADSP-2126x SHARC Processor Hardware Reference
FSDIV
– 1
= 0. The value of
FSDIV
divisor can be used as a
FSDIV
SPORTx_CLK
, given the
FSDIV
node and