Writing To An External Device Or Memory - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

The order of 8 to 32-bit data packing is shown in
received is [
7:0
scheme is shown in the third column of the table.

Table 8-1
data reads and writes.
Table 8-1. Packing Sequence for 32-Bit Data
Transfer
First
Second
Third
Fourth

Writing to an External Device or Memory

The parallel port has a two stage data FIFO for transmitting data (
The first stage (
nal memory via the DMA controller or a core write. The data in
moved to the second 32-bit register,
interface to the external pins. Once a full word is transferred out of
data is moved to
TXPP

The
PPTRAN
enable writes to it.
The order of 32- to 8-bit data unpacking is shown in
byte transferred from
32-bit to 16-bit unpacking scheme is shown in column three of the table.
ADSP-2126x SHARC Processor Hardware Reference
], second [ ] and so on. The 16- to 32-bit packing
15:8
does not show
ALE
AD7–0, 8-bit to 32-bit
(8-bit bus, LSW first)
Word 1; bits 7–0
Word 1; bits 15–8
Word 1; bits 23–16
Word 1; bits 31–24
) is a 32-bit register that receives data from the inter-
TXPP
, if
PPSO TXPP
bit of the
PPCTL
is [
PPSO 7:0
Table
cycles; it shows only the order of the
AD15–0, 16-bit to 32-bit
(16-bit bus, LSW first)
Word 1; bits 15–0
Word 1; bits 31–16
. The
PPSO PPSO
is not empty.
register must be set to one in order to
], the second [
15:8
Parallel Port
8-1. The first byte
TXPP
is
TXPP
register provides an
PPSO
Table 8-2. The first
] and so on. The
).
,
8-7