#define SRU_PIN0
#define SRU_PBEN0
#define PCG_CTLA1
#define PCG_CTLA0
#define PCG_CTLB1
#define PCG_CTLB0
#define PCG_PW
/* SRU Definitions */
#define PCG_CLKA_O
#define PCG_CLKB_P
#define PCG_FSB_P
#define PBEN_HIGH_Of
//Bit Positions
#define PCG_EXTB_I
#define DAI_PB02
#define PCG_PWB
/* Bit Definitions */
#define ENCLKA
#define ENFSB
#define ENCLKB
#define CLKBSOURCE
#define FSBSOURCE
/* Main code section */
.global _main; /* Make main global to be accessed by ISR */
.section/pm seg_pmco;
_main:
/*Route PCG Channel A clock to PCG Channel B Input via SRU*/
r0 = (PCG_CLKA_O<<PCG_EXTB_I);
dm(SRU_CLK3) = r0;
ADSP-2126x SHARC Processor Hardware Reference
0x2460
0x2478
0x24C1
0x24C0
0x24C3
0x24C2
0x24C4
0x1c
0x39
0x3B
0x01
5
6
16
0x80000000
0x40000000
0x80000000
0x80000000
0x40000000
Precision Clock Generator
13-15
Need help?
Do you have a question about the ADSP-21261 SHARC and is the answer not in the manual?
Questions and answers