Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 769

Table A-44. PCG_PW Register (Bypass Mode)
Bits Name
0
1
15–2
16
17
31–18
1 In bypass mode, Bits 15-2 and Bits 31-18 are ignored.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCG_PW (0x24C4)
0
PWFSB
Pulse Width Frame Sync B
15 14 13 12 11 10
0
Figure A-61. PCG_PW Register (Normal Mode)
ADSP-2126x SHARC Processor Hardware Reference
Description
STROBEA One Shot Frame Sync A. Frame sync is a pulse with duration
equal to one period of MISCA2_I signal repeating at the
beginning of every frame.
Note: This is valid in bypass mode only.
INVFSA Active Low Frame Sync Select for Frame Sync A. Selects an
active low FS if set, (= 1) or active high FS if cleared, (= 0).
1
Reserved
STROBEB One Shot Frame Sync B. Frame Sync is a pulse with duration
equal to one period of MISCA3_I signal repeating at the
beginning of every frame.
Note: This is valid in bypass mode only.
INVFSB Active Low Frame Sync Select. Selects an active low FS if set,
(= 1) or active high FS if cleared, (= 0).
1
Reserved
0 0 0 0 0 0 0
9 8
0 0 0 0 0 0 0
Registers Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
PWFSA
Pulse Width Frame
Sync A
A-147