Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 177

Table 3-25. System Registers Read and Effect Latencies (Cont'd)
Register
STKYY
USTAT1
USTAT2
USTAT3
USTAT4
1 Note that the number of cycles it takes for the effect latencies for different registers (for example,
MODE1, MODE2) given above is just a maximum value. Different bits in these registers have
different effect latencies, ranging from 0 to the maximum value given in the table. Users can (a)
write code that does not have any dependency on the above effect latencies or can (b) write code
such that there are "NOPs" for those many cycles as specified in the table.
ADSP-2126x SHARC Processor Hardware Reference
Contents
Sticky status flags
User-defined status flags
User-defined status flags
User-defined status flags
User-defined status flags
Program Sequencer
Bits Read
Latency
32 0
32 0
32 0
32 0
32 0
Maximum
Effect
1
Latency
1
0
0
0
0
3-65