Restrictions; Cycle Count Functionality (Emuclk) Register; Silicon Revision Id; Jtag Related Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Restrictions

If a breakpoint interrupt comes at a point when the program is coming
out of an interrupt service routine (ISR) of a prior breakpoint, then in
some cases the breakpoint status will not reflect that the second break-
point interrupt has occurred.
If an instruction address breakpoint is placed just after a short loop, then a
spurious breakpoint is generated.

Cycle Count Functionality (EMUCLK) Register

When the emulator is connected to the DSP and the processor is single
stepping, extra cycles are used by the emulator and this can make it seem
as though the instructions are taking more cycles then the should. You can
see the actual cycle time of the processor (without the emulator) by poll-
ing the
EMUCLK
seen while the core is in user space.

Silicon Revision ID

The ADSP-2126x contains an 8-bit revision ID (
Identification register. This register can be read by using the JTAG
instruction
EMUPID

JTAG Related Registers

Information in this section describes public (JTAG) registers.
information, see "Emulation Registers" on page A-46.
ADSP-2126x SHARC Processor Hardware Reference
and registers. The processor cycle count can be
EMUCLK2
. The I/O address of
JTAG Test Emulation Port
), or the Device
REVPID
is 0x30026.
REVPID
For more
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