Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 581

active low width pulse waveform is measured at the
internally-clocked timer is used to determine the period and pulse width
of externally-applied rectangular waveforms. The Period and Width regis-
ters are read-only in
measurements are with respect to a clock frequency of
Figure 14-4 shows a flow diagram for
timer resets words of the count in the
0x0000 0001 and does not start counting until it detects the leading edge
on the
TIMERx
TMxPRD
CLOCK
SET
TMxOVF
BIT
2
LEADING
EDGE
DETECT
TMRx
Figure 14-4. Timer Flow Diagram – WDTH_CAP Mode
ADSP-2126x SHARC Processor Hardware Reference
mode. The period and pulse width
WDTH_CAP
signal.
DATA BUS
TMxCNT
RESET
TMxOVF
TIMERx
mode. In this mode, the
WDTH_CAP
register value to
TMxCNT
TMxW
1
INTERRUPT
LOGIC
2
PRDCNT
Peripheral Timer
signal. The
/2.
CCLK
1
TRAILING
TMRx
EDGE
DETECT
INTERRUPT
14-11